Traditional memory bit cells are well known and widely used. In a conventional six transistor (6T) bitcell, in order to write into the bitcell, a Write Line (WL) needs to go high and the zero is written either from the Bit Line (BL) or the Bit Line Bar (BLB) side by pulling either the BL or the BLB low depending on the data. The READ happens by sensing the differential between the BL and BLB when the WL goes high. In a conventional eight transistor (8T) bitcell the WRITE operation is same as in the 6T bitcell. The READ operation happens when the RWL goes high. The Read Bit Line (RBL) is precharged high. If the node B is high, then the RBL will go low, otherwise it will stay high.
In a conventional 8T bitcell used for dual port Static Random Access Memories (SRAMs), one can read and write through port A and can read and write through port B as well. That is why this bitcell is called a dual port bitcell. Neither read nor write is single ended. Please note that this bitcell has eight transistors.
As the single ended read is becoming more popular due to the complexity of the technology, the 2R2W (two read two write) bitcell came into existence. In this bitcell, the read operation is single ended. The price paid in terms of area is evident from the fact that it is now a 12T bitcell. For writing in to the bitcell through port A, WWLA (Write Word Line for port A) turns ON and the data is written through WBLA/WBLAB (Write Bitline for port A/Write Bitline for port A Bar). For reading through port A, RWLA (Read Word Line for port A) turn ON and the bitcell content is read through RBLA (Read Bit Line for port A). Similarly, for writing in to the bitcell through port B, WWLB turns ON and the data is written through WBLB/WBLBB. For reading through port B, RWLB turns ON and the bitcell content is read through RBLB.
If one wants to have one additional write port, it will need additional two transistors (a pair of passgates) and a pair of bitlines. If one wants to have one additional read port, it will need additional two transistors and one additional read bitline.
The 6T single port bitcell with single ended read and single ended write and the corresponding architecture have been described in our previous U.S. Provisional patent application 62/098,492 dated Dec. 31, 2014. One can do a single ended read and single ended write to function as a single port memory using a 6T bitcell.